When the wiring structure in a semiconductor device has multiple levels, it is difficult to reduce the vertical geometrical size of a contact hole in the same ratio as the horizontal geometrical size thereof, so an increase of aspect ratio results for contact holes to lower levels of wiring or to the substrate. Accordingly, a conventional metal wire layer forming method has several problems such as a non-planarity, a poor step coverage, residual metal shorts, a low yield or a deteriorated reliability. In attempting to avoid problems with the use of aluminum for metal wire layers and contact plugs, such as problems with the migration of aluminum into silicon during subsequent high-temperature processing steps, considerable attention has been given to using refractory metals instead, such as tungsten, for forming the wire layer and contact plugs to lower levels of the multiple-level wiring.
Recently, as a new wiring technology for solving such problems, a technology for simultaneously attaining a metal contact hole filling and a metal wiring called Dual Damascene has been widely used. The Dual Damascene technology generally adopts a blanket-CVD of tungsten (W). FIGS. 1A through 1E are cross-sectional views for explaining the method for forming the semiconductor metal wiring layer according to a conventional Dual Damascene.
Referring to FIG. 1A, an insulating layer 12 is formed on a silicon substrate 10 having a step difference structure (not shown) formed therein, and then an oxide is deposited thereonto a predetermined thickness as an interlevel dielectric film 14. Subsequently, a first photoresist pattern 16 for forming a metal wiring layer is formed on the resultant structure and then the interlevel dielectric film 14 is etched using the first photoresist pattern 16 as a mask.
Referring to FIG. 1B, after removing the first photoresist pattern 16, a second photoresist pattern 18 for forming a contact hole is formed on the resultant structure. Subsequently, the interlevel dielectric film 14 and the insulating layer 12 are etched using the second photoresist pattern 18 as a mask.
Referring to FIG. 1C, after removing the second photoresist pattern 18, titanium (Ti) and titanium nitride (TiN) are sequentially deposited on the resultant structure by a sputtering method or a CVD method to form an ohmic layer 19 and a barrier layer 20, respectively.
Referring to FIG. 1D, blanket-tungsten (W) is deposited on the resultant structure having the barrier layer 20 formed thereon by a CVD method to form a tungsten layer 21.
Referring to FIG. 1E, the tungsten layer 21 formed on the interlevel dielectric film 14 is etched by a chemical mechanical polishing (CMP) method, leaving filled metal contact holes and level tungsten wiring.
The aforementioned method for forming a metal wiring layer according to the conventional Dual Damascene technology involves several problems. First, since the specific resistance of tungsten used as a metal plug is higher than that of aluminum (Al: 2.7.about.3.3 .mu..omega.cm, W: 5.about.6 .mu..omega.cm), the metal wiring forming speed becomes slow. Second, since the grain of tungsten is grown in a columnar structure, a seam is formed within the contact hole due to an incoherence. Therefore, the etch rate becomes fast in the seam portion during a subsequent CMP process, thereby producing a V-shaped valley in the central portion of a tungsten metal plug or wire, as shown in FIG. 1E. Third, since tungsten is harder than aluminum, and since tungsten is deposited to a thickness of several thousand angstroms in order to compensate for its higher resistivity, when tungsten is etched by the CMP method the processing time is long compared with that for aluminum.
Attempts have been made to use a metal wiring layer of aluminum and aluminum contact plugs from that metal wiring layer to titanium contacts used on silicon devices to establish good ohmic contact. These attempts have included the use of a titanium nitride barrier layer over the titanium contacts for preventing the migration of aluminum into the silicon devices during subsequent high-temperature processing steps. The attempts have not been particularly successful, because voids tend to occur quite frequently in the aluminum metal wiring and contact hole portions. Accordingly, the use of aluminum for metal wiring layers and contact plugs has continued to be considered unacceptable for commercial manufacturing of semiconductor devices having a multiple-level wiring structure.
The inventor postulated that inhomogeneous growth of chemical-vapor-deposited aluminum on the TiN barrier layer is responsible for the voids in the aluminum metal wiring and contact hole portions. It was previously known in a general way that when CVD-Al is deposited on TiN film, CVD-Al having a very coarse surface is grown. This is because titanium has a catalytic function, but titanium for nucleation is present inhomogeneously at the surface of the TiN film. Since CVD-Al is more rapidly grown where titanium is present on the surface of TiN film and is less rapidly grown elsewhere, the growth becomes inhomogeneous, coarsening the surface of the CVD-Al. To avoid inhomogeneous growth of aluminum on the TiN barrier layer, the inventor reasoned, the amount of titanium present for nucleation at the surface of the TiN film must be made more uniform. The inventor reasoned that the preference would be to provide ample titanium over the entire surface of the TiN barrier layer to support homogeneous growth of CVD-Al, so the homogeneous growth of CVD-Al would be rapid.